DocumentCode :
2960395
Title :
Reduced complexity symbol detectors with parallel structures
Author :
Erfanian, Javan A. ; Pasupathy, Subbarayan ; Gulak, Glenn
Author_Institution :
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
fYear :
1990
fDate :
2-5 Dec 1990
Firstpage :
704
Abstract :
A practical realization of fixed-delay symbol-by-symbol detection for noisy and time-dispersive channels is discussed. The mapping of the symbol-detection algorithm onto a fully parallel array structure is described. Through systematic reformulations of the algorithm, a number of simplifications are introduced that avoid the computation of exponentials and reduce the number of multiplications to be performed at the expense of introducing a comparable number of simple operations of addition, comparison, and table lookup, the result is shown to be a simplified parallel symbol (SPS) detector. A comparison of the SPS detector and Viterbi detector shows that the former achieves a slightly better performance at low SNR and the latter is simpler in complexity for high values of the delay constraint; otherwise, the two are comparable in complexity and performance
Keywords :
digital signal processing chips; parallel architectures; signal detection; fixed-delay symbol-by-symbol detection; noisy channels; parallel array structure; performance; reduced complexity symbol detector; symbol-detection algorithm; time-dispersive channels; Delay; Detection algorithms; Detectors; Error probability; High performance computing; Intersymbol interference; Java; Maximum likelihood detection; Maximum likelihood estimation; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Global Telecommunications Conference, 1990, and Exhibition. 'Communications: Connecting the Future', GLOBECOM '90., IEEE
Conference_Location :
San Diego, CA
Print_ISBN :
0-87942-632-2
Type :
conf
DOI :
10.1109/GLOCOM.1990.116598
Filename :
116598
Link To Document :
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