A novel approach for system level synthesis of multi-core system architectures from TPG models

A multi-processor system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a novel approach to synthesize multi-core system architectures from Task Precedence Graphs (TPG) models. The front end engine applies efficient algorithm for scheduling and communication contention resolving to obtain the optimal multi-core system architecture in terms of number of processor cores, number of busses, task-to-processor/channel-to-bus mapping, optimal schedule, and hardware-software (HW-SW) partition. The scheduling and mapping algorithms produce the optimality of mapping tasks onto cores. The partitioning technique reduces the overall execution time and number of buses among the cores. The back end engine generates a SystemC simulation model using a well-known commercial tool model generation library. The viability and potential of the proposed algorithms are demonstrated by a case study and extensive experimental results to conclude that the proposed approach is an efficient scheme to obtain the optimality of scheduling, mapping and partitioning with hard and large task graph problems.