Intra- and Inter-Processors Memory Size Estimation for Multithreaded MPSoC Modeled in Simulink

Target architectures for Simulink-based flows have been generally fixed and partitioned manually. The quality of the results or the final performance of the MPSoC depends heavily on the adaptation of the architecture to the needs in terms of processing performance as well as the efficiency of the communication protocols. The processing horse power determination is not limited to the selection of appropriate processors, but also to the amount of memory needed to run the software tasks. Moreover, inter-processors buffer memories and their sizes are as critical and require attention and focus to avoid communication loss or bottlenecks.