SystemC-defined SIMD instructions for high performance SoC architectures

This work presents a SystemC-based design of custom SIMD instructions for accelerating media and telecom codes on a next-generation configurable, extensible processor. The SS_SPARC processing platform, incorporates a generic vector unit which can be extended with pipelined, SIMD computation units (datapaths) designed either with established (RTL-based) or in this case, hybrid (SystemC-RTL) methodologies. This work elaborates on a custom methodology for automatically encapsulating the data-parallel sections of the MPEG-4 XviD the G723.1 and G729A reference codes into a SystemC wrapper which is subsequently synthesized to RTL with a commercial SystemC-synthesis tool. The resulting RTL is then attached to the exposed vector unit of the SS_SPARC engine. We present results from a standard-cell RTL synthesis campaign and the VLSI implementation of a high-end (8-contexts, 256 bit) and a low-end (2-context, 128 bit) configuration of the vector engine for the workloads of interest.