An 11Gb/s CMOS Demultiplexer Using Redundant Multi-valued Logic

This paper proposes an 11 Gb/s CMOS demultiplexer (DEMUX) using a redundant multi-valued logic (RMVL). Owing to the redundant multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than a conventional binary logic. The implemented DEMUX consists of eight integrators and each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The proposed circuit was simulated by HSPICE. The technology we used is the 0.35 um standard CMOS process. The maximum data rate is 11 Gb/s and the average power consumption is 69.43 mW.