Title :
Design of a fully-static differential low-power CMOS flip-flop
Author :
Yalcin, T. ; Ismailoglu, N.
Author_Institution :
Tubitak Bilten, Ankara, Turkey
Abstract :
A fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson (see IEEE Jour. of Solid-State Circuits, vol. 32, no. 1, p. 62-9, 1997) in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The add-and-delay structure is chosen since it is a widely used block in digital signal processing. The proposed structure is shown to consume less power and occupy a smaller silicon area. It has the additional advantage of being easier to merge with pass-transistor logic structures
Keywords :
CMOS logic circuits; delay circuits; flip-flops; low-power electronics; add/delay circuit; differential CMOS flip-flop; digital signal processing; fully-static flip-flop structure; low-power CMOS flip-flop; power consumption; silicon area reduction; speed comparison; CMOS logic circuits; CMOS technology; Clocks; Delay; Flip-flops; Pulse width modulation inverters; Silicon; Software libraries; Switches; Voltage;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777870
