DocumentCode
2960974
Title
Geometric-mean based current-mode CMOS multiplier/divider
Author
López-Martín, Antonio J. ; Carlosena, Alfonso
Author_Institution
Dept. Ingenieria Electr. y Electron., Univ. Publica de Navarra, Spain
Volume
1
fYear
1999
fDate
36342
Firstpage
342
Abstract
A novel current-mode analog multiplier/divider based on a voltage-translinear implementation of a geometric-mean circuit is presented, featuring favorable precision and wide dynamic range. It is suitable for standard CMOS fabrication and can be successfully applied in a wide range of analog systems. Two versions, based on stacked and up-down voltage-translinear loops, respectively, are described and verified by simulation
Keywords
CMOS analogue integrated circuits; analogue multipliers; analogue processing circuits; current-mode circuits; dividing circuits; CMOS multiplier/divider; analog multiplier/divider; current-mode multiplier/divider; geometric-mean circuit; stacked voltage-translinear loops; standard CMOS fabrication; up-down voltage-translinear loops; voltage-translinear implementation; wide dynamic range; CMOS technology; Circuit simulation; Circuit topology; Detectors; Dynamic range; Fabrication; MOSFETs; Phase detection; Transconductance; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.777873
Filename
777873
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