DocumentCode
2961070
Title
Load adaptive, high efficiency, switched capacitor intermediate bus converter
Author
Oraw, Bradley ; Ayyanar, Rajapandian
Author_Institution
Arizona State Univ., Tempe
fYear
2007
fDate
Sept. 30 2007-Oct. 4 2007
Firstpage
628
Lastpage
635
Abstract
A new non-isolated Intermediate Bus Converter is proposed using a divide-by-4 switched capacitor network. A load adaptive scheme is designed that maximizes the efficiency for all load currents. Detailed analysis using steady-state charge transfer is provided with a static charge constraint concept for degenerate switched capacitor networks. Simple average models for output impedance, capacitor and switch RMS currents, and efficiency are defined. A bus stability criterion is established, and a novel current splitting technique is introduced that reduces the capacitors´ RMS currents. A 300 W 48 V to 12 V prototype is designed using a provided efficiency-specified design procedure that achieves 96%-97% over the full range of load current, 1 A-25 A.
Keywords
capacitor switching; power convertors; current 1 A to 25 A; current splitting technique; divide-by-4 switched capacitor network; efficiency 96 percent to 97 percent; high efficiency intermediate bus converter; load adaptive intermediate bus converter; power 300 W; static charge constraint; steady-state charge transfer; switched capacitor intermediate bus converter; voltage 12 V; voltage 48 V; Costs; Impedance; MOSFETs; Magnetic switching; Parasitic capacitance; Switched capacitor networks; Switches; Switching converters; Switching frequency; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Telecommunications Energy Conference, 2007. INTELEC 2007. 29th International
Conference_Location
Rome
Print_ISBN
978-1-4244-1627-1
Electronic_ISBN
978-1-4244-1628-8
Type
conf
DOI
10.1109/INTLEC.2007.4448856
Filename
4448856
Link To Document