A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

Author

Frjad-Rad, R. ; Chih-Kong Ken Yang ; Horowitz, M. ; Lee, T.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1998

fDate

11-13 June 1998

Firstpage

198

Lastpage

199

Abstract

A 10-Gb/s serial link transmitter fabricated in the LSI 0.4-/spl mu/m CMOS process uses multilevel signaling (4-PAM) and a 3-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the maximum on-chip frequency set by process limitations, a 5:1 output multiplexer is used to reduce the required clock frequency to 1/5 the symbol rate. With a 3.3-V supply, the chip shows an eye opening of >200 mV after a 10-m coaxial cable in simulations.

Keywords

CMOS digital integrated circuits; coaxial cables; data communication; intersymbol interference; large scale integration; pulse amplitude modulation; telecommunication signalling; transmitters; 0.4 micron; 10 Gbit/s; 10 m; 3.3 V; 4-PAM pre-emphasis serial link transmitter; CMOS process; LSI; channel low-pass effects; clock frequency; coaxial cable; eye opening; intersymbol interference; multilevel signaling; on-chip frequency; process limitations; symbol rate; three-tap pre-emphasis filter; CMOS process; Clocks; Coaxial cables; Filters; Frequency; Intersymbol interference; Large scale integration; Multiplexing; Signal processing; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4766-8

Type

conf

DOI

10.1109/VLSIC.1998.688082

Filename

688082