Implementation of a Mixed Signal Chip for Multichannel Audio Equalizer with Sigma-delta A/D Conversion

This paper presents a multi-channel audio equalizer which hosts both a multiband filterbank module and an analog-to-digital converter (ADC) module. Each module is designed to minimize the space occupation of the ASIC. The multiband filterbank module is designed to utilize a time shared multiplier. The time shared multiplier effectively reduces the gate numbers required in implementing the multiband filterbank. The ADC module includes a single-bit second-order sigma-delta modulator and a digital decimation filter. The sigma-delta modulator operates at a clock rate of 11.29 MHz and its power consumption per channel is estimated about 20 mW including the power consumed in the reference voltage and current generation. The decimation filter is designed to give 98 dB of SNR for the ADC. The effective resolution of the ADC is enhanced to 98 dB of SNR by the incorporation of a pre FIR filter, a 2-stage cascaded integrator-comb (CIC) filter and a 30-tab FIR filter in the decimation. The design is verified with an FPGA and fabricated with a 0.35 mum CMOS technology.