A portable digital DLL architecture for CMOS interface circuits

Author

Garlepp, B.W. ; Donnelly, K.S. ; Jun Kim ; Chau, P.S. ; Zerbe, J.L. ; Huang, C. ; Tran, C.V. ; Portmann, C.L. ; Stark, D. ; Yiu-Fai Chan ; Lee, T.H. ; Horowitz, M.A.

Author_Institution

Rambus Inc., Mountain View, CA, USA

fYear

1998

fDate

11-13 June 1998

Firstpage

214

Lastpage

215

Abstract

A digital DLL was developed which achieves infinite phase range and 40 ps worst-case phase resolution at 400 MHz. The architecture uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correctors. This more easily process-portable DLL achieves jitter performance comparable to a more complex analog DLL, when placed into identical high-speed interface circuits fabricated on the same die in a 0.4 /spl mu/m CMOS process.

Keywords

CMOS digital integrated circuits; delay lock loops; synchronisation; timing circuits; timing jitter; 0.4 micron; 400 MHz; CMOS interface circuits; CMOS process; clock recovery; dual delay lines; duty cycle correctors; end-of-cycle detector; high-speed interface circuits; jitter performance; phase blenders; portable digital DLL architecture; CMOS digital integrated circuits; CMOS process; Clocks; Delay lines; Detectors; Inverters; Jitter; Phase detection; Signal resolution; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4766-8

Type

conf

DOI

10.1109/VLSIC.1998.688089

Filename

688089