Title :
Test structure for characterizing capacitance matrix of multi-layer interconnections in VLSI
Author :
Mido, T. ; Ito, H. ; Asada, K.
Author_Institution :
Dept. of Electron. Eng., Tokyo Univ., Japan
Abstract :
A compact new test structure using shift register circuits for extraction of components of the capacitance matrix of multilayer interconnections has been proposed. An extraction method for the capacitance matrix is also presented. As a result of fabrication, capacitance values obtained by measurement are in good agreement with numerical calculations. We also showed an estimation method for the measurement errors
Keywords :
VLSI; capacitance; error analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; measurement errors; shift registers; VLSI multilayer interconnections; capacitance; capacitance matrix; capacitance matrix component extraction; measurement error estimation; measurement errors; numerical calculations; shift register circuits; test structure; Capacitance measurement; Circuit testing; Clocks; Conductors; Delay estimation; Indium tin oxide; Integrated circuit interconnections; Parasitic capacitance; Shift registers; Very large scale integration;
Conference_Titel :
Microelectronic Test Structures, 1998. ICMTS 1998., Proceedings of the 1998 International Conference on
Conference_Location :
Kanazawa
Print_ISBN :
0-7803-4348-4
DOI :
10.1109/ICMTS.1998.688090
