Title :
A 2 Gb/s/pin CMOS asymmetric serial link
Author :
Kun-Yung Ken Chang ; Ellersick, W. ; Shang-Tse Chuang ; Sidiropoulos, S. ; Horowitz, M.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
Abstract :
The design of an asymmetric serial link poses a number of tradeoffs for the designer. This paper describes measurements from a 0.25 /spl mu/m CMOS test chip which show that a properly designed asymmetric link can achieve 2 Gb/s using single-ended signalling with a bit-error rate <10/sup -14/.
Keywords :
CMOS digital integrated circuits; data communication equipment; digital communication; error statistics; high-speed integrated circuits; packet switching; timing; 0.25 micron; 2 Gbit/s; BER; CMOS asymmetric serial link; CMOS test chip; bit-error rate; crossbar switches; network switches; single-ended signalling; Calibration; Clocks; Noise level; Phase locked loops; Semiconductor device measurement; Switches; Testing; Timing; Transmitters; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688091
