A LVDS Serial AER Link

Author

Miró-Amarante, L. ; Jiménez, A. ; Linares-Barranco, A. ; Gomez-Rodríguez, F. ; Paz, R. ; Jiménez, G. ; Civit, A. ; Serrano-Gotarredona, R.

Author_Institution

Univ. de Sevilla., Sevilla

fYear

2006

fDate

10-13 Dec. 2006

Firstpage

938

Lastpage

941

Abstract

Address-event-representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows to analyse a LVDS Serial AER link. The interface allows up to 0.7 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps.

Keywords

VLSI; microprocessor chips; protocols; VLSI chips; address-event-representation; asynchronous events; bio-inspired processing systems; bit rate 0.7 Gbit/s to 1.3 Gbit/s; communication protocol; high speed digital parallel bus; Clocks; Communication cables; Convolutional codes; Frequency; Magnetic noise; Noise cancellation; Pins; Protocols; Real time systems; Retina;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Conference_Location

Nice

Print_ISBN

1-4244-0395-2

Electronic_ISBN

1-4244-0395-2

Type

conf

DOI

10.1109/ICECS.2006.379944

Filename

4263522