A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology

This paper presents a continuous-time delta-sigma modulator with a resolution of 10 bits in a 10 MHz signal bandwidth. It is designed in a standard 0.18 mum CMOS technology and consumes 6 mW. A hierarchical bottom-up, multi-objective evolutionary design methodology was developed to reduce design time. It takes advantage of the Pareto-optimal performance solutions of the hierarchically decomposed lower-level sub-blocks to generate the overall Pareto-optimal set at modulator level. A 7-block hierarchical decomposition of a 640-MHz DeltaSigma modulator for 802.11a/b/g WLAN applications is implemented and optimized towards power efficiency.