Title :
Design tradeoffs in CMOS FIR filters
Author :
Nagendra, Chetana ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
FIR filtering is one of the basic operations in digital signal processing. To cope with the increasing demands on the speed of DSP processors for real-time and mobile applications, it is important to identify design techniques which help us build very high speed, low power filters. In this paper, we first investigate the effects of multiplier recoding which is a popular technique to increase the speed of multipliers. Next, we propose a method for reducing the activity factor, and hence the power consumption, of multipliers by using gated clocks. Lastly, we look at pipelining issues in multi-hundred MHz filters. In pipelined systems a large fraction of the total power is consumed by the clock circuitry. We compare the power and speed of bit, half-bit and gate level pipelining techniques in multipliers
Keywords :
CMOS digital integrated circuits; FIR filters; UHF filters; UHF integrated circuits; digital filters; integrated circuit design; pipeline processing; very high speed integrated circuits; CMOS FIR filters; DSP processors; activity factor; bit level pipelining techniques; clock circuitry; design tradeoffs; digital signal processing; gate level pipelining techniques; gated clocks; half-bit level pipelining techniques; mobile applications; multi-hundred MHz filters; multiplier recoding; power consumption; real-time applications; total power; very high speed low power filters; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Counting circuits; Delay; Digital signal processing; Filtering; Finite impulse response filter; Pipeline processing;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1996. ICASSP-96. Conference Proceedings., 1996 IEEE International Conference on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3192-3
DOI :
10.1109/ICASSP.1996.550572
