Title :
A negative Vth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories
Author :
Takeuchi, K. ; Satoh, S. ; Tanaka, T. ; Imamiya, K. ; Sakui, K.
Author_Institution :
Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
This paper proposes a new NAND flash memory and related novel circuit techniques that suppress the program disturb and realize a smaller cell size with minimum array noise. The memory cell realizes a LOCOS width reduction of 20%. This architecture is essential for a scaled STI cell because of the improved program disturb. The proposed column latch and Vcc-bitline shield sensing method enable excellent noise immunity and decrease the Vth distribution from 1.2 V to 0.6 V. They also improve device reliability.
Keywords :
MOS memory circuits; NAND circuits; flash memories; integrated circuit noise; integrated circuit reliability; memory architecture; 0.6 to 1.2 V; LOCOS width reduction; NAND flash memories; Vcc-bitline shield sensing method; cell size reduction; column latch; device reliability; highly reliable flash memories; highly scalable memory; minimum array noise; negative Vth cell architecture; noise immunity; program disturb suppression; scaled STI cell; threshold voltage distribution; Capacitance; Circuits; Costs; Joining processes; Leakage current; MOS devices; Manufacturing; Space vector pulse width modulation; Threshold voltage;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688097
