Title :
Low power AES clock recovery circuit for wireless applications
Author :
Goldman, Stanley J.
Author_Institution :
Goldman Res., Dallas, TX, USA
Abstract :
An AES-EBU digital audio format compliant clock recovery circuit has been fabricated in an 0.18μm CMOS technology. The hybrid coarse and fine tune architecture achieves power dissipation as low as 9 mW and an area of only 0.6 mm2. The circuit has low jitter that was measured at 0.3% peak to peak. This low level of jitter minimizes the associated D/A noise when converting to an audio output.
Keywords :
CMOS integrated circuits; jitter; logic circuits; low-power electronics; AES-EBU digital audio format; CMOS technology; jitter; low power AES clock recovery circuit; size 0.18 micron; wireless application; CMOS technology; Circuit optimization; Clocks; Delay; Frequency; Jitter; Latches; Optical receivers; Ring oscillators; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems Workshop,(DCAS), 2009 IEEE Dallas
Conference_Location :
Richardson, TX
Print_ISBN :
978-1-4244-5483-9
Electronic_ISBN :
978-1-4244-5484-6
DOI :
10.1109/DCAS.2009.5505723
