Elimination of spurious noise due to time-to-digital converter

We propose an improved architecture of a multi-GHz all-digital phase-locked loop (ADPLL) that is free from spurious tones caused by the finite resolution of the phase detection process. These tones appear at the RF output when the synthesized frequency is very close to the integer-N multiple of the reference frequency. The phase detection in the ADPLL is performed by a time-to-digital converter (TDC), whose typical resolution of 10-30 ps is sufficient for the GSM-quality RF operation. While the TDC quantization noise does not normally produce significant phase noise degradation, the near-integer-N condition makes the loop ill-behaved such that the total quantization energy falls close to dc and will not get filtered by the loop filter. The proposed solution of randomizing the TDC quantization noise is verified through comprehensive and detailed simulations.