M-array VLSI architecture for order statistic filters

The order statistic filter is an important nonlinear filter for many image processing applications. We propose several simplified algorithms for the VLSI implementation of an order statistic filter. Specifically, we propose: (1) a simplified algorithm to reduce the chip area of an order statistic filter; (2) a simplified algorithm using fewer components compared with the Murthy and Swamy´s (see IEEE Transactions on Signal Processing, vol.40, no.5, p.1241-52, 1992) results to integrate two r-bit order statistic filters into an (r+1)-bit order statistic filter; and (3) a scheme for 2-D order statistic filter implementation. In this scheme a large ROM is replaced by very few logic components. In summary, our schemes reduce the chip area of an order statistic filter because much fewer components are used compared with the Murthy and Swamy´s results