Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining

As integrated circuits technology enters into interconnect-centric nanometer regime, it will be impossible to carry cross-chip signals in a single clock cycle and interconnect pipelining becomes an acceptable solution beyond traditional buffer-insertion based interconnect systems. This paper performed a detailed analysis for the bit error rate (BER) of two kinds of interconnect pipelining approaches, and find that the BER is unusually high for some cases. Here the cause of the high BER has been analyzed, and a method to deal with it is proposed. A comparative study of the two interconnect pipelining approaches is also presented in this paper, which will help exploring trade-offs between number of sequential elements inserted and the probability of bit-error during data transmission.