Title :
A self-reference read scheme for a 1T/1C FeRAM
Author :
Yamada, J. ; Miwa, T. ; Koike, H. ; Toyoshima, H.
Author_Institution :
Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan
Abstract :
This paper describes a self-reference read scheme for use with 1T/1C FeRAMs. It is able to overcome the reference voltage problem faced by conventional 1T/1C FeRAMs without the use of any reference cells. The proposed scheme employs a memory cell that is accessed twice, and it uses this cell to generate a reference voltage. This self-generated reference voltage is automatically kept between read bit line voltages, which correspond to stored data ("1" and "0"). We have designed and fabricated a test device, and confirmed the viability of the read scheme.
Keywords :
cellular arrays; ferroelectric storage; integrated memory circuits; random-access storage; 1T/1C FeRAM; ferroelectric memories; memory cell; one-transistor one-capacitor cell; read bit line voltages; reference voltage problem; self-generated reference voltage; self-reference read scheme; viability; Capacitors; Circuits; Fatigue; Ferroelectric films; Ferroelectric materials; National electric code; Nonvolatile memory; Parasitic capacitance; Random access memory; Voltage;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688099
