Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing

A leakage power minimization method in nanoscale CMOS circuits by transistor sizing in non-critical paths is presented. It is shown that a small increase in delay by transistor downsizing of non-critical paths can provide a significant reduction in leakage power. Moreover, nonlinear dependence of leakage current on width (due to inverse narrow width effects) can be exploited to minimize leakage power at non-minimum widths. A 64-bit carry-lookahead adder, with carry blocks optimized for speed and sum blocks minimized for leakage power, achieves a reduction in leakage power by about 25%.