DocumentCode :
2962154
Title :
A new method for extracting the capacitance coupling coefficients of sub-0.5-μm flash memory cells in the negative gate bias mode
Author :
Haraguchi, Kazuya ; Kume, H. ; Ushiyama, M. ; Ohkura, M.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
fYear :
1998
fDate :
23-26 Mar 1998
Firstpage :
229
Lastpage :
233
Abstract :
A new method for extracting the capacitance coupling coefficients of sub-0.5-μm flash memory cells under a negative gate bias is proposed. In contrast to previously developed methods, this method is not affected by the source region dopant profile. Hence, it has the potential to be applied continuously to flash memory cells with reduced dimensions. Using a reference device eliminates the need to make assumptions concerning the electron transport mechanism. Also, another easy method for extracting the gate capacitance coupling coefficient is proposed to provide confirmation
Keywords :
EPROM; capacitance; electron mobility; integrated circuit modelling; integrated circuit testing; capacitance coupling coefficients; capacitance coupling coefficients extraction; electron transport mechanism; flash memory cell dimensions; flash memory cells; gate capacitance coupling coefficient; negative gate bias; negative gate bias mode; reference device; source region dopant profile; Capacitance; Electrons; Flash memory; Flash memory cells; Fluctuations; Laboratories; Leakage current; Nonvolatile memory; Tunneling; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 1998. ICMTS 1998., Proceedings of the 1998 International Conference on
Conference_Location :
Kanazawa
Print_ISBN :
0-7803-4348-4
Type :
conf
DOI :
10.1109/ICMTS.1998.688100
Filename :
688100
Link To Document :
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