Title :
Comparison of two architectures for implementation of the discrete cosine transform
Author :
Sundsb, Ingil ; Hansen, Gisle Lokken ; Aas, Einar J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Norwegian Inst. of Technol., Trondheim, Norway
Abstract :
A new DCT architecture developed by Mou and Jutand (1991) is compared to an architecture based on distributed arithmetic with ROMs realized as random logic. Both architectures have been implemented in 0.8 μm CMOS technology and optimized with different constraints on area and timing. The results reveal that for HDTV applications the design with distributed arithmetic is superior, with lower power consumption and less than half the chip area
Keywords :
CMOS digital integrated circuits; digital arithmetic; digital signal processing chips; discrete cosine transforms; high definition television; read-only storage; timing; transform coding; video coding; 0.8 micron; CMOS technology; DCT architecture; HDTV applications; ROM; area constraints; chip area; discrete cosine transform; distributed arithmetic; power consumption; random logic; timing constraints; video coding; Arithmetic; CMOS technology; Computer architecture; Computer science; Discrete cosine transforms; Encoding; Energy consumption; HDTV; Image coding; Matrix decomposition;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1996. ICASSP-96. Conference Proceedings., 1996 IEEE International Conference on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3192-3
DOI :
10.1109/ICASSP.1996.550575
