DocumentCode :
2962218
Title :
FPGA optimized packet-switched NoC using split and merge primitives
Author :
Yutian Huan ; DeHon, Andre
Author_Institution :
Electr. & Syst. Eng., Univ. of Pennsylvania, Philadelphia, PA, USA
fYear :
2012
fDate :
10-12 Dec. 2012
Firstpage :
47
Lastpage :
52
Abstract :
Due to their different cost structures, the architecture of switches for an FPGA packet-switched Network-on-a-Chip (NoC) should differ from their ASIC counterparts. The CONNECT network recently demonstrated several ways in which packet-switched FPGA NoCs should differ from ASIC NoCs. However, they also concluded that pipelining was not appropriate for the FPGA switches.We show that the Split-Merge switch architecture is more amenable to pipelining on FPGAs, achieving 300MHz operation-up to three times the frequency and throughput of the CONNECT switches-with only 13-37% more area. Furthermore, we show that the Split-Merge switches are at least as efficient at routing traffic as the CONNECT switches, meaning the 2-3× frequency translates directly into two to three times the application performance.
Keywords :
application specific integrated circuits; field programmable gate arrays; network-on-chip; packet switching; semiconductor switches; ASIC NoC; ASIC counterparts; CONNECT network; CONNECT switches; FPGA optimized packet-switched NoC; FPGA packet-switched network-on-a-chip; FPGA pipelining; FPGA switches; cost structures; merge primitive; packet-switched FPGA NoC; routing traffic; split primitive; split-merge switch architecture; split-merge switches; Application specific integrated circuits; Control systems; Delay; Field programmable gate arrays; Pipeline processing; Pipelines; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology (FPT), 2012 International Conference on
Conference_Location :
Seoul
Print_ISBN :
978-1-4673-2846-3
Electronic_ISBN :
978-1-4673-2844-9
Type :
conf
DOI :
10.1109/FPT.2012.6412110
Filename :
6412110
Link To Document :
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