Title :
A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback
Author :
Radjen, Dejan ; Andreani, Pietro ; Anderson, Martin ; Sundström, Lars
Author_Institution :
Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden
Abstract :
This paper presents a low-power multi-bit continuous-time ΔΣ modulator with a new approach to clock jitter reduction utilizing switched-capacitor-resistor techniques. The modulator features a 3rd order loop filter, implemented with active RC integrators, and 3-bit quantizer and feedback DACs. The ΔΣ modulator has been implemented in a 65nm CMOS process and tested. It achieves a peak SNDR of 70 dB in a 125 kHz signal bandwidth while consuming 380 μW. The combination of a high-order loop filter and multi-bit quantizer allows for a high resolution at a low sampling frequency of 4MHz, corresponding to an oversampling ratio of 16.
Keywords :
CMOS integrated circuits; clocks; delta-sigma modulation; jitter; low-power electronics; switched capacitor networks; 3rd order loop filter; CMOS process; DSCR feedback; active RC integrators; bandwidth 125 kHz; feedback DAC; frequency 4 MHz; high-order loop filter; low-power multibit continuous-time ΔΣ modulator; multibit quantizer; power 380 muW; reduced clock jitter sensitivity; size 65 nm; switched-capacitor-resistor techniques; word length 3 bit; CMOS integrated circuits; Modulation; Resistors; Semiconductor device measurement; Switches; Switching circuits; Voltage measurement;
Conference_Titel :
NORCHIP, 2011
Conference_Location :
Lund
Print_ISBN :
978-1-4577-0514-4
Electronic_ISBN :
978-1-4577-0515-1
DOI :
10.1109/NORCHP.2011.6126701
