A Novel Bootstrapped Switch Design, Applied in a 400 MHz Clocked ΔΣ ADC

Author

Cornelissens, Koen ; Steyaert, Michiel

Author_Institution

K.U.Leuven, Leuven

fYear

2006

fDate

10-13 Dec. 2006

Firstpage

1156

Lastpage

1159

Abstract

This paper presents a switch bootstrapping technique for very high sampling frequencies. The circuit has been implemented in a switched capacitor delta sigma A/D converter operating at 400 MHz in a 0.18 μm CMOS technology. The high sampling frequency allows to use a high oversampling ratio, resulting in a SNR of 53 dB and signal bandwidth of 3.125 MHz with a simple singleloop second order topology. Measured SNDR is 47.5 dB, while the core power consumption is 12 mW.

Keywords

CMOS integrated circuits; UHF integrated circuits; bootstrap circuits; sigma-delta modulation; signal sampling; switched capacitor networks; CMOS technology; DeltaSigma ADC; bandwidth 3.125 MHz; bootstrapped switch design; frequency 400 MHz; oversampling ratio; power 12 mW; singleloop second order topology; size 0.18 mum; switch bootstrapping technique; switched capacitor delta sigma A/D converter; Bandwidth; CMOS technology; Clocks; Frequency; Sampling methods; Switched capacitor circuits; Switches; Switching circuits; Switching converters; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Conference_Location

Nice

Print_ISBN

1-4244-0394-4

Electronic_ISBN

1-4244-0395-2

Type

conf

DOI

10.1109/ICECS.2006.379645

Filename

4263577