A Novel Bootstrapped Switch Design, Applied in a 400 MHz Clocked ΔΣ ADC

This paper presents a switch bootstrapping technique for very high sampling frequencies. The circuit has been implemented in a switched capacitor delta sigma A/D converter operating at 400 MHz in a 0.18 μm CMOS technology. The high sampling frequency allows to use a high oversampling ratio, resulting in a SNR of 53 dB and signal bandwidth of 3.125 MHz with a simple singleloop second order topology. Measured SNDR is 47.5 dB, while the core power consumption is 12 mW.