Track-and-Latch Comparator Design Using Associations of MOS Transistors and Characterization

This paper addresses the design of a track-and-latch switched analog comparator in a pre-diffused array of digital - i.e. minimum length - transistors. The mapping of each original single transistor of the circuit into an equivalent trapezoidal association of digital transistors (TAT) is analyzed. This analog module was analyzed, designed and prototyped in AMS 0.35 mum CMOS technology. Experimental results are presented, in order to validate the methodology. The comparator has a sensibility of 184 mV, maximum frequency of 18 MHz and a current consumption of 288 muA.