Supply regulation techniques for phase-locked loops

Phase-locked loops (PLLs) which employ voltage regulators for low supply-noise sensitivity often rely upon significant decoupling capacitance to suppress negative (Gnd) supply noise and maintain low jitter. This paper compares various supply regulation techniques on the basis of their ability to reject noise from both positive and negative supplies. A novel replica-based dual-supply regulation technique is proposed which allows for significant reduction in decoupling capacitance for a given supply noise rejection. Comparison simulations in a 90 nm CMOS technology show the replica-based dual-supply regulation technique achieving a worst case noise sensitivity of 1.6 rad/V, an improvement of 7.5 rad/V (15.1 dB) relative to a single-supply replica-based regulator topology. At 4.7 GHz, the replica-based dual-supply regulated PLL consumes 11 mW from a 1.2 V supply.