Address Generation Techniques for Conflict Free Parallel Memory Accessing in FFT Architectures

Speeding up FFT computations is critical for today´s real time systems targeting signal processing and telecommunication applications. Aiming at the performance improvement and the efficiency of FFT architectures this paper presents an address generation technique which enables a b-radix processing stage to access in parallel b memory banks without conflicts and leads to increasing the speedup of the algorithm by a factor of b. The address generation can be realized in each b-radix stage by the use of look up tables of size O(b²) bits. The proposed technique is cost efficient and leads to the design of FFT architectures of high speed and high sustained throughput.