DocumentCode
2962481
Title
A low voltage low power CMOS analog multiplier
Author
Miremadi, Amir H. ; Ayatollahi, Ahmad ; Abrishamifar, Adib
Author_Institution
Dept. of Electr. Eng., Islamic Azad Univ., Tehran, Iran
fYear
2011
fDate
14-15 Nov. 2011
Firstpage
1
Lastpage
4
Abstract
This paper presents a single low-voltage CMOS analog multiplier with low-power consumption. It consists of four voltage adders and a multiplier core. The proposed circuit is simulated with HSPICE and simulation results have shown that, under single 0.9V supply voltage, the circuit has smaller than 1.8% linearity error and 0.88% THD under the maximum-scale input 400mVp-p at both inputs. The quiescent power consumption is 58μW and the -3dB bandwidth is 70MHz.
Keywords
CMOS analogue integrated circuits; SPICE; adders; analogue multipliers; circuit simulation; harmonic distortion; low-power electronics; HSPICE; THD; bandwidth 70 MHz; circuit simulation; four voltage adders; linearity error; low voltage low power CMOS analog multiplier; low-power consumption; low-voltage CMOS analog multiplier; maximum-scale input; multiplier core; power 58 muW; quiescent power consumption; supply voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
NORCHIP, 2011
Conference_Location
Lund
Print_ISBN
978-1-4577-0514-4
Electronic_ISBN
978-1-4577-0515-1
Type
conf
DOI
10.1109/NORCHP.2011.6126712
Filename
6126712
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