Comparison and IIP2 analysis of two wideband Balun-LNAs designed in 65nm CMOS

Author

Zhu, Lin ; Liliebladh, Martin

Author_Institution

Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden

fYear

2011

fDate

14-15 Nov. 2011

Firstpage

1

Lastpage

4

Abstract

Two wideband Balun-LNA configurations have been designed in 65nm COMS technology. Both of them employ a single-to-differential (S-to-D) conversion topology composed of a common gate (CG) amplifying stage and a common source (CS) stage, providing output balancing and noise and distortion cancelling. One is inductorless and the other one exploits gain-boosting current-balancing topology. With 2.5V and 2.5V/1.8V supply the LNAs achieve voltage gains of 24.5dB and 22.8dB, noise figures of below or close to 3dB, input second-order intercept points (IIP2) of 31dB and 41.8dB, respectively. In addition, the sensitivity of IIP2 is deeply investigated.

Keywords

CMOS analogue integrated circuits; baluns; integrated circuit design; low noise amplifiers; CG amplifying stage; CMOS technology; CS stage; IIP2 analysis; S-to-D conversion topology; common gate amplifying stage; common source stage; gain 22.8 dB; gain 24.5 dB; gain-boosting current-balancing topology; input second-order intercept points; single-to-differential conversion topology; size 65 nm; voltage 1.8 V; voltage 2.5 V; wideband balun-LNA configurations; Balun-LNA; Monte Carlo; common gate; common source; gain-boosting current-balancing; low noise amplifiers (LNA); noise-cancelling; second-order input-referred intercept point (IIP2); self-biasing; single-to-differential (S-to-D);

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP, 2011

Conference_Location

Lund

Print_ISBN

978-1-4577-0514-4

Electronic_ISBN

978-1-4577-0515-1

Type

conf

DOI

10.1109/NORCHP.2011.6126716

Filename

6126716