ASAP-a 2D DFT VLSI processor and architecture

Author

Mellott, J.D. ; Lewis, Michael ; Taylor, Fred ; Coffield, P.

Author_Institution

Florida Univ., Gainesville, FL, USA

Volume

6

fYear

1996

fDate

7-10 May 1996

Firstpage

3280

Abstract

We examine the use of an innovation, called the logarithmic residue number system or LRNS, as an alternative to conventional DSP processors for implementing multiply-accumulate (MAC) operations. The Athena Sensor Arithmetic Processor (ASAP) is a custom VLSI multiprocessor chip based on the LRNS. The fabricated ASAP device is an LRNS “vector-processor on a chip” capable of achieving MAC bandwidth-area ratios far greater than a conventional processor. The paper develops the scientific foundations upon which the LRNS is based, develops the ASAP architecture, and demonstrates its use in the design of a 231×231 two dimensional FFT having a one hundred frame per second bandwidth

Keywords

VLSI; digital signal processing chips; discrete Fourier transforms; multiprocessing systems; residue number systems; vector processor systems; 2D DFT VLSI architecture; 2D DFT VLSI processor; ASAP architecture; Athena Sensor Arithmetic Processor; DSP processors; LRNS; bandwidth-area ratios; chip vector-processor; custom VLSI multiprocessor chip; logarithmic residue number system; multiply-accumulate operations; signal processing applications; two dimensional FFT; Adders; Arithmetic; Bandwidth; Cathode ray tubes; Computer architecture; Digital signal processing chips; Signal processing; Technological innovation; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1996. ICASSP-96. Conference Proceedings., 1996 IEEE International Conference on

Conference_Location

Atlanta, GA

ISSN

1520-6149

Print_ISBN

0-7803-3192-3

Type

conf

DOI

10.1109/ICASSP.1996.550577

Filename

550577