Title :
A high-performance architecture for training Viola-Jones object detectors
Author :
Lo, Chieh ; Chow, Peter
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
The object detection algorithm developed by Viola and Jones has become very popular due to its high quality and detection speed. However, the complexity of the computation required to train a detector makes it difficult to develop and test potential improvements to this algorithm. Furthermore, improving or training new detectors in the field is problematic. In this paper, we present a flexible FPGA architecture to accelerate this training process. The proposed systolic architecture is constructed to provide high throughput and make efficient use of the available external memory bandwidth. The design is implemented on a Xilinx ML605 development platform running at 200 MHz and obtains a 14-fold speed-up over a multi-threaded OpenCV implementation running on a high-end processor.
Keywords :
computational complexity; field programmable gate arrays; multi-threading; object detection; parallel architectures; Viola-Jones object detector training; Xilinx ML605 development platform; computational complexity; external memory bandwidth; flexible FPGA architecture; high-end processor; high-performance architecture; multithreaded OpenCV implementation; object detection algorithm; systolic architecture; Acceleration; Detectors; Engines; Field programmable gate arrays; Hardware; Random access memory; Training;
Conference_Titel :
Field-Programmable Technology (FPT), 2012 International Conference on
Conference_Location :
Seoul
Print_ISBN :
978-1-4673-2846-3
Electronic_ISBN :
978-1-4673-2844-9
DOI :
10.1109/FPT.2012.6412131
