A high-performance architecture for training Viola-Jones object detectors

The object detection algorithm developed by Viola and Jones has become very popular due to its high quality and detection speed. However, the complexity of the computation required to train a detector makes it difficult to develop and test potential improvements to this algorithm. Furthermore, improving or training new detectors in the field is problematic. In this paper, we present a flexible FPGA architecture to accelerate this training process. The proposed systolic architecture is constructed to provide high throughput and make efficient use of the available external memory bandwidth. The design is implemented on a Xilinx ML605 development platform running at 200 MHz and obtains a 14-fold speed-up over a multi-threaded OpenCV implementation running on a high-end processor.