A divide-by-three regenerative frequency divider using a subharmonic mixer

Author

Jackson, Brad R. ; Saavedra, Carlos E.

Author_Institution

Dept. of Electr. & Comput. Eng., Gigahertz Integrated Circuits Group, Queen´´s Univ., Kingston, ON, Canada

fYear

2011

fDate

14-15 Nov. 2011

Firstpage

1

Lastpage

4

Abstract

A regenerative frequency divider topology is used with a ×2 subharmonic mixer to realize a divide-by-three frequency divider. The circuit accepts input signals in the range of 5.2 GHz to 5.5 GHz and produces signals from 1.73 GHz to 1.83 GHz. Measured results show a maximum conversion gain of 0 dB and at least a 30 dB suppression of all undesired harmonic components at the output. The circuit core consumes 44 mW of dc power and ideas are provided on how to reduce the power draw. The chip was fabricated on a standard 0.13-μm CMOS process and it occupies an area of 1.0 mm² including bonding pads.

Keywords

CMOS analogue integrated circuits; MMIC mixers; UHF mixers; frequency dividers; CMOS process; DC power; bonding pad; divide-by-three regenerative frequency divider topology; frequency 1.73 GHz to 1.83 GHz; frequency 5.2 GHz to 5.5 GHz; maximum conversion gain; power 44 mW; power draw reduction; size 0.13 mum; subharmonic mixer; undesired harmonic component; Bonding; Frequency measurement; Harmonic analysis; Logic gates; Mirrors; Mixers; Phase measurement; CMOS analog integrated circuits; divide-by-3; frequency divider; monolithic microwave integrated circuit (MMIC); regenerative divider;

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP, 2011

Conference_Location

Lund

Print_ISBN

978-1-4577-0514-4

Electronic_ISBN

978-1-4577-0515-1

Type

conf

DOI

10.1109/NORCHP.2011.6126726

Filename

6126726