DocumentCode
2962797
Title
Area constraint propagation in high level synthesis
Author
Nane, Razvan ; Sima, Vlad Mihai ; Bertels, Koen
Author_Institution
Comput. Eng. Lab., Delft Univ. of Technol., Delft, Netherlands
fYear
2012
fDate
10-12 Dec. 2012
Firstpage
247
Lastpage
252
Abstract
Hardware compilers which generate hardware descriptions from high-level languages are rapidly gaining in popularity. These generated descriptions are used to obtain fast implementations of software/hardware solutions in heterogeneous computing platforms. However, to obtain optimal solutions under certain platform constraints, we need intelligent hardware compilers that choose proper values for the different design parameters automatically. In this paper, we present a two-step algorithm to optimize the performance for different area constraints. The design parameters under investigation are the maximum unroll factor and the optimal allocation of resource types. Experimental results show that generated solutions are mapped into the available area at an occupancy rate between 74% and 99%. Furthermore, these solutions provide the best execution time when compared to the other solutions that satisfy the same area constraint. Finally, a reduction in design time of 42x on average can be achieved when these parameters are chosen by the compiler compared to manually selecting them.
Keywords
field programmable gate arrays; high level languages; high level synthesis; multiprocessing systems; area constraint propagation; hardware compilers; heterogeneous computing; high level synthesis; high-level languages; Algorithm design and analysis; Engines; Hardware; IP networks; Kernel; Optimization; Parallel processing; DWARV 2.0; FPGA; HLS; area constraint; unroll;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Technology (FPT), 2012 International Conference on
Conference_Location
Seoul
Print_ISBN
978-1-4673-2846-3
Electronic_ISBN
978-1-4673-2844-9
Type
conf
DOI
10.1109/FPT.2012.6412143
Filename
6412143
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