Title :
A new hardware coprocessor for accelerating Notification-Oriented applications
Author :
Peters, Edward ; Jasinski, R.P. ; Pedroni, Volnei A. ; Simao, Jean M.
Author_Institution :
Grad. Sch. in Electr. Eng. & Ind. Comput. Sci. (CPGEI), Univ. Fed. Univ. of Technol.-Parana (UTFPR), Curitiba, Brazil
Abstract :
This paper presents a new hardware coprocessor to accelerate applications developed using the Notification-Oriented Paradigm (NOP). A NOP application presents the advantages of both event-based programming and declarative programming, enabling higher lever software development, improving code reuse, and reducing the number of unnecessary computations. Because a NOP application is composed of a network of small computational entities communicating only when needed, it is a good candidate for a direct hardware implementation. In order to investigate this assumption, we have created a coprocessor that is able to run existing NOP applications. The coprocessor was developed in VHDL and tested in FPGAs and provided a decrease of 96% in the number of clock cycles, compared to a purely software implementation.
Keywords :
coprocessors; electronic engineering computing; field programmable gate arrays; hardware description languages; program compilers; software engineering; FPGA; NOP application; VHDL; clock cycles; code reuse; computational entity; declarative programming; event-based programming; hardware coprocessor; hardware implementation; higher level software development; notification-oriented applications; notification-oriented paradigm; software implementation; Clocks; Coprocessors; Field programmable gate arrays; Hardware; Monitoring; Programming; Software;
Conference_Titel :
Field-Programmable Technology (FPT), 2012 International Conference on
Conference_Location :
Seoul
Print_ISBN :
978-1-4673-2846-3
Electronic_ISBN :
978-1-4673-2844-9
DOI :
10.1109/FPT.2012.6412145