Analog CMOS implementation of a bursting oscillator with depressing synapse

The present paper proposes an analog CMOS circuit that implements a bursting oscillator with a depressing synapse. Bursting oscillation arises as the result of interaction between a fast excitatory subsystem and a slow subsystem. We employ an analog circuit, called the hardware oregonator for emulating the Belousov-Zhabotinsky reaction as a fast subsystem and an additional circuit as a slow subsystem. We constructed a bursting oscillator circuit from two bursting cell circuits, based on the hardware oregonator with a depressing synaptic circuit. Using SPICE, we demonstrate that the circuit shows bursting oscillations and the bursting frequency can be regulated by tuning the depressing synapse circuit.