High-performance VLSI through package-level interconnects

Author

Liang, Louis ; Wilson, J.D. ; Brathwaite, N. ; Mosley, L.E. ; Love, D.

Author_Institution

Intel Corp., Santa Clara, CA, USA

fYear

1989

fDate

22-24 May 1989

Firstpage

518

Lastpage

523

Abstract

A packaging technique utilizing controlled-collapse chip connection to integrate two existing high-performance VLSI devices into a single pin-grid-array (PGA) package is described. The design and layout of the multilayer ceramic package, electrical and thermal performance, and future enhancements are discussed. The performance of the package is compared to that of a companion two-cavity, wire-bonded evaluation package. The potential use of the packaging technique as a substitute for wafer-level integration is examined

Keywords

VLSI; integrated circuit technology; packaging; PGA package; controlled-collapse chip connection; electrical performance; high-performance VLSI devices; multilayer ceramic package; package-level interconnects; packaging technique; single pin-grid-array package; thermal performance; two-cavity package; wafer-level integration; wire-bonded evaluation package; Bonding; Ceramics; Costs; Dielectric substrates; Dielectric thin films; Electronics packaging; Flip chip; Integrated circuit interconnections; Very large scale integration; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components Conference, 1989. Proceedings., 39th

Conference_Location

Houston, TX

Type

conf

DOI

10.1109/ECC.1989.77799

Filename

77799