DocumentCode
2963033
Title
Optimal-depth circuits for prefix computation and addition
Author
Yeh, Chi-Hsiang ; Varvarigos, E.A. ; Parhami, B.
Author_Institution
Dept. of Electr. & Comput. Eng., Queen´´s Univ., Kingston, Ont., Canada
Volume
2
fYear
2000
fDate
Oct. 29 2000-Nov. 1 2000
Firstpage
1349
Abstract
Addition and prefix computation are among the most fundamental problems in arithmetic and algebraic computation. In this paper, we present efficient circuits for performing prefix computation and addition with small depth and size and flexible fan-in (i.e., the maximum fan-in can be selected as a small constant or a larger constant/nonconstant number). In particular, we show that any prefix operation of n inputs can be computed using a circuit of fan-in k, depth log/sub k/n+o(log/sub k/n)+O(1), gate complexity O(n), and edge complexity O(n log/sup d-1**...*d-1/n), for any constant integer d. We show that the sum of two n-bit numbers can be found using an AND-OR circuit of fan-in k, depth log/sub k/n+o(log/sub k/n)+O(1), and edge complexity O(n(log/sup d-1**...*d-1/n)/sup 2/), for any constant integer d. In particular, the depths of our circuits for prefix computation and addition are optimal within a factor of 1+o(1), for any fan-in k=n/sup o(1)/.
Keywords
computational complexity; digital arithmetic; logic circuits; AND-OR circuit; addition computation; algebraic computation; digital arithmetic; edge complexity; flexible fan-in; gate complexity; optimal-depth circuits; prefix computation; Circuits; Delay; Digital arithmetic;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-6514-3
Type
conf
DOI
10.1109/ACSSC.2000.911212
Filename
911212
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