A digital PLL with a multi-delay coarse-fine TDC

Author

Wu, Ying ; Lu, Ping ; Andreani, Pietro

Author_Institution

Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden

fYear

2011

fDate

14-15 Nov. 2011

Firstpage

1

Lastpage

4

Abstract

A 5GHz digital frequency synthesizer achieving a low noise for wireless RF application is presented. This architecture uses a multi-delay coarse-fine Time-to-Digital Converter (TDC) to achieve both the large detection range and fine resolution. A Digitally Controlled Oscillator (DCO) based on capacitive degeneration in LC-Tank is also implemented. The DCO achieves frequency quantization step of 300 Hz without any dithering. Simulated phase noise at 5 GHz carrier frequency is -125 and -151 dBc/Hz at 1 MHz and 20 MHz offset, respectively. The Digital phase-locked loop (DPLL) is realized in 90nm CMOS process and consumes 14mA from a 1.2V supply.

Keywords

CMOS digital integrated circuits; digital phase locked loops; frequency synthesizers; oscillators; phase noise; quantisation (signal); time-digital conversion; CMOS process; DCO; DPLL; LC-tank; capacitive degeneration; carrier frequency; detection range; digital PLL; digital frequency synthesizer; digital phase-locked loop; digitally controlled oscillator; dithering; fine resolution; frequency quantization step; low noise; multidelay coarse-fine TDC; multidelay coarse-fine time-to-digital converter; simulated phase noise; wireless RF application; Decoding;

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP, 2011

Conference_Location

Lund

Print_ISBN

978-1-4577-0514-4

Electronic_ISBN

978-1-4577-0515-1

Type

conf

DOI

10.1109/NORCHP.2011.6126745

Filename

6126745