High-speed parallel hard and soft-decision Golay decoder: algorithm and VLSI-architecture

Author

Weixun Cao

Author_Institution

Fraunhofer-Inst. for Integrated Circuits, Erlangen

Volume

6

fYear

1996

fDate

7-10 May 1996

Firstpage

3295

Abstract

An efficient algorithm and the VLSI-architecture for fast soft-decision permutation decoding of the (24,12) extended Golay code are presented. The new decoding technique consists of an optimized permutation decoding with look-ahead error-correction and a modified parity-check soft-decision decoding with reduced test patterns based on the Chase´s (1972) algorithm-2. The simulation results for the Gaussian fading channel were found to be only slightly inferior to Chase´s algorithm-2 although performing only four test patterns. A parallel VLSI-architecture is also proposed, which will allow for data rates reaching in the hundreds of Mbit/s

Keywords

Gaussian channels; Golay codes; VLSI; channel capacity; decoding; digital integrated circuits; error correction codes; fading; parallel algorithms; parallel architectures; (24,12) extended Golay code; Chase´s algorithm-2; Gaussian fading channel; VLSI-architecture; algorithm; data rates; fast soft-decision permutation decoding; high-speed parallel decision Golay decoder; look-ahead error-correction; modified parity-check soft-decision decoding; optimized permutation decoding; reduced test patterns; Circuit testing; Computer errors; Delay; Error correction; Fading; Maximum likelihood decoding; Parity check codes; Performance evaluation; Protection; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1996. ICASSP-96. Conference Proceedings., 1996 IEEE International Conference on

Conference_Location

Atlanta, GA

ISSN

1520-6149

Print_ISBN

0-7803-3192-3

Type

conf

DOI

10.1109/ICASSP.1996.550581

Filename

550581