Noise and Jitter in CMOS Digitally Controlled Delay Lines

Analysing the impact of noise sources on the random instantaneous delay of a basic CMOS delay element is important for understanding the performance of systems that employ them, like voltage controlled delay lines or buffered clock distribution networks. This paper presents a model for the analysis of noise induced jitter in CMOS delay cells and delay lines. Because the increasing switching noise levels is becoming a serious impairment to the reliable use of analogue controlled devices inside high frequency digital VLSI circuits, this work focus primarily on digitally controlled delay lines. For these circuits, the output capacitance and drivability of delay elements are key parameters for the design of low jitter delay lines. Simulation results are presented for a 0.35mum CMOS technology.