Author :
Arnal, V. ; Farcy, A. ; Aimadeddine, M. ; Jousseaume, V. ; Gosset, L.G. ; Guillan, J. ; Assous, M. ; Favennec, L. ; Zenasni, A. ; David, T. ; Hamioud, K. ; Chapelon, L.L. ; Jourdan, N. ; Vanypre, T. ; Mourier, T. ; Chausse, P. ; Maitrejean, S. ; Guedj, C.
Abstract :
Integrated circuits are more and more impacted by interconnect performance. As size reaches nanometric dimensions, changes in materials aim at performing a reliable and compliant technology with a maximum capability to reduce delay time and power consumption. At the 32 nm node, k value reduction of existing porous SiOCH and optimization of metallization with thin barrier, conformal seed and plating should mitigate RC and offer an improvement compared to current materials of the 45 nm node.
Keywords :
circuit optimisation; dielectric materials; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; nanoelectronics; organic compounds; porous materials; BEOL; delay time reduction; high signal propagation performance; interconnect performance; metallization optimization; power consumption reduction; reliability enhancement; size 32 nm; Capacitance; Conductivity; Contact resistance; Copper; Delay effects; Dielectrics; Integrated circuit interconnections; Materials reliability; Signal processing; Wires;
