• DocumentCode
    2963458
  • Title

    The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology

  • Author

    Kitada, H. ; Suzuki, T. ; Kimura, T. ; Kudo, H. ; Ochimizu, H. ; Okano, S. ; Tsukune, A. ; Suda, S. ; Sakai, S. ; Ohtsuka, N. ; Tabira, T. ; Shirasu, T. ; Sakamoto, M. ; Matsuura, A. ; Asada, Y. ; Nakamura, T.

  • Author_Institution
    Fujitsu Labs. Ltd, Atsugi
  • fYear
    2007
  • fDate
    4-6 June 2007
  • Firstpage
    10
  • Lastpage
    12
  • Abstract
    We tried to evaluate and predict the RC delay variability beyond the 45 nm copper interconnects technologies. The RC delay variability as a normalized delay time distribution, is caused by the line width/height variations due to the manufacturing process fluctuations. In order to evaluate the influence of the resistivity size effect precisely, we improved Fuchs-Sondheimer (F-S) and Mayadas-Shatzkes (M-S) models, in order to include the line height dependence of copper grain size, and applied it in the evaluation of the RC delay variability based on the SPICE simulation. In our results, we found that the RC delay variability in the 45nm node technology was relatively small, weakly dependent on the grid size and line height, and almost not affected by the size effect. On the contrary, in the 32 nm technology, the RC delay variability was about 2 times larger than the case ignoring the size effect and reached to the 20% of the average delay time at 3000 grid with 10% of line size fluctuation. In the 32 nm technology, the line height dependence of the RC delay variability was also strong and increased with decreasing line height. The influence of line height dependence of grain size reached about 1/5 or more of the total size effect in the RC delay variability.
  • Keywords
    SPICE; copper; electrical resistivity; grain size; integrated circuit interconnections; Cu; Fuchs-Sondheimer models; Mayadas-Shatzkes models; RC delay variability; SPICE simulation; ULSI devices; copper interconnects; line height dependence; manufacturing process fluctuations; normalized delay time distribution; resistivity size effect; size 32 nm; Circuit simulation; Conductivity; Copper; Delay effects; Electric resistance; Fluctuations; Grain boundaries; Grain size; Laboratories; SPICE;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    International Interconnect Technology Conference, IEEE 2007
  • Conference_Location
    Burlingame, CA
  • Print_ISBN
    1-4244-1069-X
  • Electronic_ISBN
    1-4244-1070-3
  • Type

    conf

  • DOI
    10.1109/IITC.2007.382333
  • Filename
    4263645