RNIW: a novel general-purpose DSP architecture

High-sped advanced multimedia communication require greater parallelism in the traditional general-purpose DSP architecture. Some RISC architectures can provide enough processing capability comparable to the traditional general-purpose DSP architecture but are not adequate for new multimedia applications. While the very long instruction word (VLIW) architecture has been proved to be a very good approach to this problem, the main disadvantages are the limitation of the hardware resource compared to the complexity of multiple functional units and the code size explosion when a program does not offer enough parallelism at the instruction level. We propose a novel RISC architecture, the RISC plus Normal Instruction Word (RNIW), for DSP. This architecture allows the load FIFOs to increase the data throughput, dynamic linking instruction to pipeline the data between the register groups, and sub-word partition to increase the parallelism. The parallelism has a better cost-performance ratio than the VLIW architecture and is easier for VLSI implementation