Title :
A study of trap related drain lag effects in InP HFETs
Author :
Gautier-Levine, A. ; Audren, P. ; Post, G. ; Favennec, M.P. ; Dumas, J.M.
Author_Institution :
France Telecom, CNET, Bagneux, France
Abstract :
The drain lag effect is a low frequency parasitic response of field effect transistors on III-V semiconductors. HFET devices were fabricated with InP semiconductor and quaternary lattice-matched compound channels, respectively. From the study of the drain lag value of these two types of devices, the importance of proper technological processes is emphasized
Keywords :
III-V semiconductors; electron traps; field effect transistors; indium compounds; integrated optoelectronics; HFETs; III-V semiconductors; InP; low frequency parasitic response; quaternary lattice-matched compound channels; technological processes; trap related drain lag effects; Electron devices; Electron traps; FETs; Frequency; HEMTs; Impedance; Indium phosphide; MODFETs; Pulse measurements; Threshold voltage;
Conference_Titel :
Indium Phosphide and Related Materials, 1996. IPRM '96., Eighth International Conference on
Conference_Location :
Schwabisch-Gmund
Print_ISBN :
0-7803-3283-0
DOI :
10.1109/ICIPRM.1996.492382
