A Highly Reliable Cu Interconnect Technology for Memory Device

Author

Lee, H.-B. ; Hong, J.-W. ; Seong, G.J. ; Lee, J.-M. ; Park, H. ; Baek, J.M. ; Choi, K.-I. ; Park, B.-L. ; Bae, J.-Y. ; Choi, G.H. ; Kim, S.T. ; Chung, U.I. ; Moon, J.T. ; Oh, J.H. ; Son, J.H. ; Jung, J.H. ; Hah, S. ; Lee, S.Y.

Author_Institution

Samsung Electron. Co. Ltd., Yongin

fYear

2007

fDate

4-6 June 2007

Firstpage

64

Lastpage

66

Abstract

This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50 nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50 nm trench pattern, which are lower resistance than Al and good reliabilities.

Keywords

electroplating; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated memory circuits; Cu; electroplating process; highly reliable interconnect lines; interconnect technology; memory device; metallization; optimized iPVD barrier-seed process; process integration; Conductivity; Delay; Energy management; Etching; Hafnium; Large scale integration; Metallization; Moon; Silicon compounds; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

International Interconnect Technology Conference, IEEE 2007

Conference_Location

Burlingame, CA

Print_ISBN

1-4244-1069-X

Electronic_ISBN

1-4244-1070-3

Type

conf

DOI

10.1109/IITC.2007.382350

Filename

4263662