Author :
Harada, T. ; Ueki, A. ; Tomita, K. ; Hashimoto, K. ; Shibata, J. ; Okamura, H. ; Yoshikawa, K. ; Iseki, T. ; Higashi, M. ; Maejima, S. ; Nomura, K. ; Goto, K. ; Shono, T. ; Muranaka, S. ; Torazawa, N. ; Hirao, S. ; Matsumoto, M. ; Sasaki, T. ; Matsumoto,
Abstract :
Dual damascene Cu interconnects with Keff below 2.0 have been demonstrated for the first time. Air gaps between Cu lines were formed with a low K SiOC film in a carefully designed manner. CoWP cap layers were introduced to protect the Cu lines and to eliminate a dielectric liner layer. In addition, AGE (Air Gap Exclusion) was applied to solve crucial problems related to the air gaps. Keff of 1.9 was obtained at 65 nm design rule, which surpassed by far ITRS target (2.5~2.8) for hp 45. It was also confirmed that leakage current between lines was suppressed by the formation of the air gaps.
Keywords :
cobalt alloys; copper; integrated circuit design; integrated circuit interconnections; leakage currents; low-k dielectric thin films; nanoelectronics; phosphorus alloys; protective coatings; silicon compounds; tungsten alloys; CoWP; Cu; SiOC; air gap exclusion; air gap formation; design rules; dual damascene copper interconnects; extremely low Keff copper interconnects; leakage current; size 65 nm; Air gaps; Delay; Dielectrics; Electric variables; Etching; Leakage current; Protection; Resists; Space technology; Ultra large scale integration;
